Hardware Intership #1

Title : IP 2110 Stream Analyzer

Target : Electronics engineer

Referent : Lionel Decelle

In-house competence centers: FPGA / Network

Job description :

SMPTE 2110 is a suite of standards from the Society of Motion Picture and Television Engineers (SMPTE) that describes how to send digital media over an IP network.

Deltacast (https://www.deltacast.tv/) offers PCIe capture and playout cards to support these video-over-IP transport formats.

Within the framework of these solutions, the work consists in developing a module capable of identifying and listing the streams circulating on the network upstream of capture, in order to offer assistance to the infrastructure manager and the development team.

The following points will be addressed:

• Study of the various protocols involved.
• Development of a VHDL module to analyze and log the various packets seen on the network.
• Development of a module for processing and presenting the data collected, enabling effective discrimination of the flows detected.

Hardware Intership #2

Title : FPGA Development Intern – IP10 CoDec Implementation

Target : Electronics engineer

In-house competence centers : FPGA / Video / Compression

Job description :

We are looking for a motivated and technically competent intern to join our development team. The intern will work closely with our engineers to design and implement an IP10 CoDec (encoder-decoder) system on an FPGA. This is an excellent opportunity for students or recent graduates to gain hands-on experience in FPGA development, digital signal processing and communication systems.

The following points will be addressed :

• Implement the IP10 CoDec algorithm on an FPGA platform.
• Collaborate with the team to optimize the design in terms of performance, power and resource utilization.
• Perform simulations and tests of the IP10 CoDec implementation to ensure functionality and compliance with project specifications.
• Analyze and debug hardware design problems, providing solutions and improvements.
• Contribute to the documentation of design, test procedures and results.
• Provide team with updates on progress and technical challenges.

Hardware Intership #3

Title : FPGA Development Intern – AXI4-MM FIFO with CDC

Target : Electronics engineer

In-house competence centers : FPGA / SoC

Job description :

The intern will work closely with our engineers to design and implement a new IP Core (for internal use) that combines FIFO and clock domain switching functionality for an AXI4-MM bus. This is an excellent opportunity for students or recent graduates to gain hands-on experience in FPGA development and in the development of an IP Core intended to be used in the context of a standard bus.

The following points will be addressed :

• Implement the IP Core on an FPGA platform.
• Collaborate with the team to optimize the design for performance, power, and resource utilization.
• Conduct simulations and testing of the IP Core implementation to ensure functionality and compliance with project specifications.
• Analyze and debug hardware design issues, providing solutions and enhancements.
• Contribute to the documentation of the design, testing procedures, and results.
• Present progress updates and technical challenges to the team.

If you are interested in one or more of our internship/TFE topics, please do not hesitate to request a full description of the work or other information using the form below (mentioning the topic number).